In conventional output buffer circuits coupled to a common external bus, a problem occurs during "power down" and "power up" of the power supply rails of selected buffer circuits and during "hot insertion" of the output buffer circuits. During partial system power down of selected output buffer circuits, the output bus may remain active, driven by other output buffer circuits. In NWELL CMOS technology, the high potential level signals appearing at the output of a powered down output buffer circuit may forward bias the parasitic PN junction diode between the P type substrate PSUB and the NWELL of the P channel or PMOS pullup output transistor. The NWELL of the PMOS pullup transistor is in turn coupled to the powered down high potential power rail VCC. This leakage current may recharge the high potential power rail and turn on the output buffer circuit or selected internal nodes providing paths to the low potential power rail GND or high potential power rail VCC through the output buffer circuit. The undesirable results include loading the external bus, causing "bus contention", degrading signals, and causing possible false signals on the external output bus. Ideally, the powered down output buffer circuit should remain a high impedance at the output, isolating the external bus from the powered down output buffer circuit power rails.
A disadvantage of existing solutions for avoiding this leakage path to the VCC power rail for powered down output buffer circuits is that they prevent the use of full swing CMOS buffer circuits. According to one solution, bipolar transistors are used for the output pullup transistors in a bipolar or BICMOS output buffer circuit. While the bipolar output pullup transistors isolate internal nodes from the external output bus, they are not capable of pulling the output node to the power rail potential levels. As a result the noise margins of the system are reduced and additionally, the bipolar transistors consume static current. According to another solution an enhancement mode N channel or NMOS transistor is used for the output pullup transistor instead of a PMOS transistor. The enhancement mode NMOS pullup transistor similarly introduces a threshold voltage drop and is unable to pull the output node to the voltage level of the high potential power rail VCC.
A similar problem is encountered in multiple output buffer circuit systems with mismatched or incompatible power supplies. Some of the subsystems and output buffer circuits driving the external output bus are coupled to a first power supply while other subsystems and output buffer circuits are coupled to a second power supply at a different voltage level. A current problem exists in systems combining 5 volt standard power supply circuits with the new JEDEC Standard 8-1A 3.3 volt power supply circuits. A 5 volt signal on the common bus driven by a 5 volt standard output buffer circuit may cause a leakage current path to the lower potential 3.3 volt power rail of the 3.3 v standard output buffer circuit through the PN junction at the drain to NWELL forming a parasitic P+D/NWELL diode through the PMOS output pullup transistor. Similar problems may occur in 3.3 v/5 v and 5 v/3.3 v translators incorporated in the multiple power supply system.
To provide further background, in 1992 the Joint Electron Device Engineering Council (JEDEC) of the Electronic Industries Association (EIA) adopted a new low voltage integrated circuit standard based on a 3.3 v power supply. This new low voltage standard is designated the JEDEC Standard 8-1A and is commonly known as the 3 v standard. The new JEDEC Standard 8-1A at nominal 3.3 v is to be contrasted with the conventional integrated circuit JEDEC Standards 18 and 20 for a 5 v power supply. The 3.3 v and 5 v standards are incompatible with respect to voltage levels of the respective power supplies and the logic high and low potential level signals generated by the two different circuits.
For the conventional 5 v standard and the new 3.3 v standard, the respective CMOS output buffers generally pull the output to the respective rail voltages for logic high and low potential levels under zero load or lightly loaded conditions at the output. Because of the incompatibly of the 3.3 v and 5 v standard supply voltage levels and the respective CMOS logic high and low potential level signals, translation is required for communication between 3.3 v and 5 v standard subcircuits. The new low voltage standard for a power supply at nominal 3.3 v is applicable as well for CMOS, bipolar, and BICMOS technology IC's.
Applications for the new 3.3 v standard include notebook sub-notebook, power book, hand held, and pen based portable and mobile personal computers, generally referred to as personal digital assistants or PDA's. The 3.3 v standard requires less power dissipation from the battery power supplies for longer operating life. Another advantage of the new low voltage standard is that the new CMOS logic signal high and low potential levels are compatible with bipolar TTL circuit logic signal potential levels. A difficulty with application of the new 3.3 v standard in notebook and PDA computers however is that all of the computer subsystems cannot necessarily be converted to the 3.3 v standard. For example available disk drives continue to operate on the basis of the 5 volt standard and the disk drive subsystem including the disk controller must therefore be based on the 5 v standard circuits.
In such a notebook or other PDA computer, the system board or motherboard includes the 3.3 v microprocessor (.mu.P) computer system and a plurality of ports for controlling peripherals such as a liquid crystal display (LCD) port, communications port RS232, power supply port, and external memory port. The disk drive port however may communicate with a 5 volt subsystem, namely the disk controller which operates the hard disk drive. A translator is therefore required between the 3.3 v .mu.P system and the disk drive port and 5 v disk drive controller subsystem. Such a 3.3 v to 5 v translator is provided for example by the National Semiconductor Corporation translator device LVX4245 (TM).
A problem comparable to the "power down" problem occurs with the new combined multiple power supply systems such as the combined 3.3 v and 5 v power supply subsystems and translators with multiple incompatible power supply output buffer circuits coupled to a common bus. Parasitic leakage paths may develop from the higher voltage level power supply signals applied to the output bus by an active buffer circuit to the lower voltage power supply rail of quiet output buffer circuits on the common bus. Isolation is also required to prevent power supply contention within translator circuits.